This invention relates to semiconductor devices and methods of making such devices, and more particularly to a dynamic random access memory cell and a process for manufacturing the cell.
Dynamic RAM devices are constructed in a so-called "folded bit line" arrangement to provide common mode noise rejection; folded bit line layouts are shown in U.S. Pat. No. 4,636,987, issued to Norwood et al, for example, and a modified version of a folded bit line is illustrated in U.S. Pat. Nos. 4,658,377 and 4,701,885; these patents are assigned to Texas Instruments. In the standard folded bit line layout, a true cross-point array is not possible in that every intersection of a word line and a bit line cannot have a cell; only half of these intersections can be populated with cells.
It is the principal object of this invention to provide an improved dynamic memory cell array of the type using a folded bit line layout, particularly a cell array allowing a true cross-point configuration. It is another object to provide a dynamic memory cell which is more easily constructed as a cross-point array so that the space occupied on the face of the bar is minimized. Another object is to provide a memory device of smaller size and optimum layout, and a method for making such a device.